1. Field of the Invention
This invention relates to a charge transfer device used in, for example, a transversal filter, comb filter, charge transfer type delay line, solid state imaging device and the like, and more particularly to a charge transfer device whose input section for supplying input charges is improved.
2. Description of the Related Art
In the prior art, a fill-and-spill method is known as one of signal input methods for use in the input circuit of an integrated charge transfer device (which is hereinafter referred to as CTD). The fill-and-spill method is widely used as the input method for the CTD because charges can be linearly input. The fill-and-spill method is disclosed in, for example, U.S. Pat. No. 3,986,198 and Japanese Patent publication (KOUKOKU) No. 56-49460 (corresponding to U.S. Patent Application No. 758,184).
FIG. 1 is a cross-sectional view of an input section of the prior art buried channel CTD in which the fill-and-spill method is used. FIG. 2 shows the arrangement of electrodes in FIG. 1 together with the potential states for explaining the operation of the electrodes. FIG. 3 is a waveform diagram of pulse signals used in the input section of the CTD of FIG. 1. Source region 51 is formed in the main surface area of semiconductor substrate 50, and is supplied with pulse signal .phi.S1. Signal input electrode 52 is formed on insulation film 60 and over that portion of substrate 50 which is adjacent to source region 51. Input signal V.sub.IN superposed on a D.C. bias is supplied to signal input electrode 52. Input charge storing electrode 53 for storing charges of an amount corresponding to input signal V.sub.IN is formed on insulation film 60 in position corresponding to that portion of substrate 50 which is adjacent to input electrode 52. Power source voltage V.sub.DD is applied to input charge storing electrode 53. Charge injection electrode 54 for transferring charges measured in the input section to charge transfer electrodes 55-1, 55-2, ... is formed on insulation film 60 in position corresponding to that portion of substrate 50 which is adjacent to input charge storing electrode 53. Pulse signal .phi.K is supplied to charge injection electrode 54. Charge transfer electrodes 55-1, 55-2, ... are formed on insulation film 60 in position corresponding to that portion of substrate 50 which is adjacent to charge injection electrode 54. A pulse train of .phi.1, .phi.2, .phi.2, .phi.1, .phi.1, .phi.2, .phi.2, ... are supplied to charge transfer electrodes 55-1, 55-2, 55-3, ... . A threshold voltage at which an inversion layer is formed in the surface area of substrate 50 when voltages are applied to respective electrodes 52, 53, 54, 55-1, 55-2, ... is negative. That is, the device is depletion type.
The CTD with the above construction operates as follows. At timing t1 in FIG. 3, since .phi.S1 and .phi.K are both at a low level, charges are filled in an area under signal input electrode 52 and input charge storing electrode 53 as shown in FIG. 2. At this time, the potential of source region 51 is PSL: the potential of the surface area of substrate 50 under signal input electrode 52 is P1; the potential of the surface area of substrate 50 under input charge storing electrode 53 is PD; and the potential of the surface area of substrate 50 under charge injection electrode 54 is PKL. At timing t2, .phi.S1 is set at a high level, and .phi.K is kept at the low level so that charges in portions set at a potential lower than P1 can be spilit into an area under source region 51 and an area under input charge storing electrode 53 can be filled with charges held at a potential higher than P1. At timing t3, .phi.K is set at a high level, and charges of an amount corresponding to .vertline.P1-PK.vertline. are injected as signal charge QS into an area under charge transfer electrode 55-1. In this case, PK is a potential of an area under charge injection electrode 54 which is set when .phi.K is kept at a high level. At timing t4, .phi.K is set to the low level, areas under input charge storing electrode 53 and transfer electrode 55-1 are isolated from each other by the potential of an area under charge injection electrode 54. After this, if the same operation as the cycle of t1 to t4 are repeatedly effected, signal charges corresponding to the voltage level of input signal V.sub.IN are sequentially transferred to an area under charge transfer electrode 55-1. The charge transferred to under charge transfer electrode 55-1 is sequentially transferred to the right in FIG. 1 under charge transfer electrodes 55-2, 55-3, ... in response to pulse signals .phi.1 and .phi.2.
In a case where a CTD is designed to operate on a low power source voltage, there is a lower limit to which potential .vertline.V.sub.THD .vertline. obtained when 0 V is applied to the respective gates of the CTD can be lowered. This is because charges transferred along the surface area of substrate 50 may be trapped by the effect of the surface level when .vertline.V.sub.THD .vertline. is set lower than a certain level, thus lowering the charge transfer efficiency. Further, when .vertline.V.sub.THD .vertline. is fixedly set at the lower limit and if it is required to lower the power source voltage, it will be necessary to frequently use booster circuits. That is, in a case where potential PSL becomes higher than power source voltage V.sub.DD under a condition that potential "P1-PSL" necessary for attaining a satisfactory input operation is set, it becomes necessary to raise not only the high voltage level but also the low voltage level of pulse signal .phi.S1 supplied to source region 51. For this reason, it becomes difficult to raise pulse .phi.S1. Further, if attempts are made to modify the circuit in order to reduce influence on the device characteristics due to process variation, the circuit will become complex in construction. Thus, it is extremely difficult to operate the prior art CTD on a low voltage.
As described above, in the prior art charge transfer device, a linear charge input operation cannot be attained at a low operation voltage without making the circuit construction complex.